The tendency is toward a more improved mounting density of electronic components on a printed wiring substrate. On such a printed wiring substrate, spaces are reduced between terminals for electrically connecting the electronic elements, and between wirings extending from the terminals. In order to assure reliable connections between the terminals, between the wirings, and between the terminals and wirings, a micro-wiring technology and a multi-layered wiring technology have been remarkably developed. Further, high density mounting of electronic components such as semiconductor elements is extensively promoted by making the best use of the micro-wiring and multi-layered wiring technologies.
Generally, in a popular semiconductor element such as a resin encapsulated semiconductor element, a bare chip is mounted on a lead frame, and the bare chip and an inner lead of the lead frame are resin-molded. The bare chip is an integrated circuit and includes passive and active elements mounted on a silicon substrate. Various methods such as a pin-insert mounting type method and a face mounting type method are available for mounting the resin-encapsulated semiconductor elements.
In the foregoing resin-encapsulated semiconductor elements, since outer leads project from a resin mold, they are very difficult to be mounted in a very packed manner. In order to overcome this problem, a semiconductor device having a multiple chip module structure (called the “MCM” hereinafter) is being the center of attention at present. In this structure, a plurality of bare chips are attached on one common printed circuit and are covered by a protective resin layer. Thereafter, the wiring substrate is attached to a lead frame, and both the bare chips and the wiring substrate are resin-molded. The bare chips are mounted on the wiring substrate using the tape-automated bonding method (TAB), chip carrier bonding method (CCB) or the like. Sometimes, bare chips are mounted on the wiring substrate using an insulating adhesive or a conductive adhesive, and bonding pads of the bare chips are electrically connected to the wiring substrate by bonding wires.
Recently, a chip size package structure (CSP) has been noted in order to improve the mounting density of electronic elements. In this structure, a bare chip is mounted on a wiring substrate which is as large as the bare chip. With a semiconductor device of the CSP structure, terminals on a front surface of a wiring substrate are electrically connected to a bonding pad of the bare chip by a primary connection electrode while terminals on a second main surface of the wiring substrate are electrically connected to an external unit using a secondary connection electrode. Solder balls, solder pastes or the like are used as the primary and second connection electrodes. Further, the foregoing semiconductor device can have a so-called three dimensional mounting structure, i.e. bare chips are arranged in a plurality of layers in a package, or a plurality of packages are laid one over after another. This further promotes high density mounting of elements.
The semiconductor device of the CSP structure seems to have the following problems.    (1) Terminals provided on the wiring substrate and wirings extending from these terminals tend to be arranged with reduced pitches therebetween, and are made of thin films having a thickness in the order of μm. If a connection electrode, e.g. a solder ball having a thickness in the order of millimeters (mm), is provided on such a thin film terminal used in order to arrange bare chips or packages in multiple layers, stress resultant from a thermal cycle tends to concentrate on a connecting region between the terminal and the connection electrode, so that the connecting region would be damaged. As a result, electric conductivity may be adversely affected, which makes it difficult to realize the three-dimensional mounting of elements.    (2) If the foregoing connecting region is thickened in order overcome the above-mentioned problem, micro fabrication of terminals and wirings becomes very difficult. This means that downsizing of semiconductor devices cannot be realized.    (3) When arranging bare chips or packages in multiple layers, additional parts should be used in order to align upper and lower bare chips, or upper and lower packages. This would cause an increase in the number of components, and change in the structure of the semiconductor device, a complicated structure, difficulty of downsizing the semiconductor device, and difficulty of the three-dimensional mounting of elements.    (4) Further, the addition of the aligning parts and the structure change of the semiconductor device would lead not only to an increase of manufacturing (assembling) processes, increase of manufacturing cost and product cost but also to reduced yield of the manufacturing process.